Simulation and Evaluation for a Network on Chip Architecture Using Ns-2

A new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future systems on chips. NOC architectures offer a packet switched communication among functional cores on the chip. NOC architectures also apply concepts from computer networks and organize on-chip communication among cores in layers similar to OSI reference model. We constructed a protomodel using a public domain network simulator ns-2 and evaluated design options for a specific NOC architecture which has a twodimensional mesh of switches. In particular, we analysed the series of simulation results about the relationship between buffer size in switch, communication load, packet delay and packet drop probability. All the results are useful for design of an appropriate switch for the NOC.